Errata - Datasheets W65C816S

Errors in the latest (September 13, 2010) datasheet from WDC:

p. 11, beneath Table 2-1

The Emulation flag should be "E", not "M"

p. 26, Table 3-1

  • Stack row: both Program Sequence Bytes columns should be 1 (JSR and JSL are listed elsewhere as absolute (absolute,X) and long addressing, not stack addressing)
  • Clarification: note that this table is merely a (simplified) summary; footnote 1 would imply that a STA abs,X instruction would take 4 cycles when M=1 (8-bit accumulator) when a page boundary is not crossed; however, STA abs,X takes 5 cycles when M=1 (whether or not a page boundary is crossed

p. 33, Table 5-4

  • The "new instruction"s are actually opcodes that are present on the WDC 65C02 and WDC 65C816, but not the NMOS 6502 (i.e. "new" to the 65C02)
  • The "old instructions with new addressing modes" are actually opcodes that are new to the 65C816 (i.e. opcodes which were not present on the WDC 65C02)
  • The new 65C816 instructions are in the "7" column, not the "6" column
  • 60: RTS should be 6 cycles, not 7
  • 82: BRL should be 4 cycles, not 3
  • B4: LDA d,x should be LDY d,x
  • B5: LDY d,x should be LDA d,x
  • B6: d,Y is listed twice
  • 87: STA [d] should be 6 cycles, not 2
  • 7A: PLY is present on the WDC 65C02 and WDC 65C816, but not the NMOS 6502, like other "new instruction"s (see above)
  • 9C: STZ a should be 4 cycles and 3 bytes, not 3 and 4
  • FC: JSR (a,x) should be 8 cycles, not 6

Clarification: the two numbers within each cell of the table are the cycle count and the instruction size (in bytes), respectively. The cycle counts assume that:

  • branches are not taken
  • no page boundary crossings (if in emulation mode)
  • the m and x flags are 1 (8-bit accumulator and index registers)
  • BRK and COP assume emulation mode
  • RTI assumes native mode

p. 34, Table 5-5

  • (a) is not a valid addressing mode for ADC; that entry should be empty, not 17
  • AND d,x should be 35, not 36
  • AND (d,x) should be 21, not 91
  • JSL should be noted as a new W65C816S instruction

p. 35, Table 5-5

  • PHB should be noted as a new W65C816S instruction
  • SBC affects the V flag (as well as the N, Z, and C flags)

p. 39, Table 5-7, Address Mode 4c.

In the Address Mode column, JSL should be 8 cycles, not 7

p. 39, Table 5-7, Address Mode 6a

In the Address Mode column, STA is listed twice

p. 42, Table 5-7, Address Mode 18

The Note column should have footnote 8, not footnote 6

p. 43, Table 5-7, Address Mode 22c

The RWB column should be 0 for cycles 3a and 3

p. 52, sections 7.2.1 and 7.2.2

Clarification: the last sentence of section 7.2.1 and (all of) section 7.2.2 regarding emulation mode are correct, but note that they are specifically referring to the case when DL is equal to zero.

p. 52, section 7.2.3

Minor typo: this section should read "…and DL is…" not "…and DL in…"

p. 53, sections 7.7.1, 7.7.2, 7.7.3, 7.7.3.1, and 7.7.3.2 (sic)

Minor typo: These are subsections of section 7.8 and should be numbered 7.8.1, 7.8.2, 7.8.3, 7.8.3.1, and 7.8.3.2

p. 53, section 7.7.2 (sic)

This is incorrect. A Bank Address is multiplexed on the data bus in emulation mode. All 24-bit addressing modes (e.g. Absolute Long and [Direct]) will work in emulation mode. It is unclear what impact the caveat as written would have for the instructions listed. (It appears to be a caveat of the 65802 rather than the 65816.)

p. 53, section 7.7.3.2 (sic)

The last sentence is unclear. One way to clarify it is:"Also, the MVP and MVN instructions can only move data within the range 0000 to 00FF (Source Bank) and 0000 to 00FF (Destination Bank) in the emulation mode

p. 53, section 7.11.2

The claim the DBR is cleared to 00 is incorrect. The DBR register is unchanged, not cleared to 00 as the datasheet claims, when a BRK or COP is executed. The reset of the caveat is correct.

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